As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as fin field-effect transistors (Fin FETs). In a Fin FET, a gate electrode is adjacent to two side surfaces of a channel region with a gate dielectric layer interposed between them.
In advanced technology nodes, the epi source or drain structure introduces issues for fin pitch scaling. The source and/or drain sheet resistance and contact resistivity can play an important role when the device area is scaling. Although large epitaxial source/drain volume is useful for device performance, but can go against yield in higher device densities, for example, in static random access memory (SRAM) chips. Solutions are required that can provide large epitaxial source/drain shapes for devices of a SRAM chip that are compatible with complementary metal-oxide-semiconductor (CMOS) flow, without adversely affecting the yield.